數字VLSI晶片設計：使用Cadence和Synopsys CAD工具.英文版（簡體書）

本書介紹如何使用Cadence和Synopsys公司的CAD工具來實際設計數字VLSI芯片。讀者通過本書可以循序漸進地學習這些CAD工具，并使用這些軟件設計出可制造的數字集成電路芯片。本書內容按集成電路的設計流程編排，包括CAD設計平臺、電路圖輸入、Verilog仿真、版圖編輯、標準單元設計、模擬和數模混合信號仿真、單元表征和建庫、Verilog綜合、抽象形式生成、布局布線及芯片總成等工具；每一工具的使用都以實例說明，最后給出了一個設計簡化MIPS微處理器的完整例子。本書可與有關集成電路設計理論的教科書配套使用，可作為高等院校有關集成電路設計理論類課程的配套教材和集成電路設計實踐類課程的教科書，也可作為集成電路設計人員的培訓教材和使用手冊。

1　Introduction
　1.1 CAD Tool Flows
1.1.1 Custom VLSI and Cell Design Flow
1.1.2 Hierarchical Cell/Block ASIC Flow
1.2 What This Book Is and Isnt
1.3 Bugs in the Tools?
1.4 Tool Setup and Execution Scripts
1.5 Typographical Conventions
2　Cadence DFII and ICFB
　2.1 Cadence Design Framework
　2.2 Starting Cadence
　2.3 Summary
3　Composer Schematic Capture
　3.1 Starting Cadence and Making a New
　Working Library
　3.2 Creating a New Cell
3.2.1 Creating the Schematic View of a Full Adder
3.2.2 Creating the Symbol View of a Full Adder
3.2.3 Creating a Two-Bit Adder Using the FullAdder Bit
　3.3 Schematics that Use Transistors
　3.4 Printing Schematics
3.4.1 Modifying PostScript Plot Files
3.5 Variable, Pin, and Cell Naming Restrictions
3.6 Summary
4 Verilog Simulation
4.1 Verflog Simulation of Composer Schematics
　4.1.1 Verilog-XL: Simulating a Schematic
4.1.2 NC_Verilog: Simulating a Schematic
4.2 Behavioral Verilog Code in Composer
4.2.1 Generating a Behavioral View
4.2.2 Simulating a Behavioral View
4.3 Stand-Alone Verilog Simulation
4.3.1 Verilog-XL
4.3.2 NC_Verilog
4.3.3 VCS
4.4 Timing in Verilog Simulations
4.4l Behavioral Versus Transistor Switch Simulation
4.4.2 Behavioral Gate Timing
4.4.3 Standard Delay Format (SDF) Timing
4.4.4 Transistor Timing
　4.5 Summary
5　Virtuoso Layout Editor
5.1 An Inverter Schematic
　5.1.1 Starting Cadence kfb
5.1.2 Making an Inverter Schematic
5.1.3 Making an Inverter Symbol
5.2 Layout for an Inverter
5.2.1 Creating a New layout View
5.2.2 Drawing an nmosTransistor
5.2.3 Drawing a pmos Transistor
5.2.4 Assembling the Inverter from the Transistor Layouts
5.2.5 Using Hierarchy in Layout
5.2.6 Virtuoso Command Overview
　……
6 Standard Cell Design Template
7 Spectre Analog Simulator
8 Cell Characterization
9 Verilog Synthesis
10 Abstract Generation
11 SOC Encounter Place and Route
12 Chip Assembly
13 Design Example
A Tool and Setup Scripts
B Scripts to Drive the Tools
C Technology and Cell Libraries
Bibliography
Index