商品簡介
A resource for engineers, this reference provides step-by-step techniques for resolving phased-locked loop (PLL) problems and challenges, from specification definition to layout generation. It includes a proven CMOS PLL design and optimization methodology that enables users to systematically assess design alternatives, predict PLL behavior, and create CMOS PLLs that meet the strictest performance requirements. Topics include: approach to CMOS PLL design, PLL fundamentals, LC-tank integrated oscillators, design of a complete PLL, and design of a frequency divider. The book was written by Quemada (researcher, IKERLAN), Bistue, and Adin (researchers, CEIT). Annotation c2009 Book News, Inc., Portland, OR (booknews.com)
