Power Integrity for Nanoscale Integrated Systems

A comprehensive examination of the procedures necessary to mitigate the emission of noise in high-voltage circuitry design

Power Integrity for Nanoscale Integrated Systems provides a thorough understanding of the impact of power integrity and noise margins on nanoscale integrated circuit design. This practical, professional guide emphasizes the impact of power integrity degradation on various analog, digital, and mixed-signal circuits in nanoscale fabrication.

• Explores the impact of power integrity (PI) degradation on circuits and systems of critical importance to nanoscale chips
• Includes detailed examples of robust circuit design with PI
• Provides hands-on training in advanced PI analysis for circuits, facilitating optimal, noise-free nanoscale integrated circuit design

Masanori Hashimoto is an Associate Professor in the department of Information Systems and Engineering, Graduate School of Information Science Technology, Osaka University. He has been working on modeling and measurement of on-chip power supply noise and signal coupling noise. Professor Hashimoto’s research interests include timing, power, and signal integrity analysis, ultra-low power design, design for reliability, performance optimization in physical design, and on-chip high-speed signaling. He has co-authored several journal articles.

Raj Nair, a consultant in IC power delivery and power integrity, is co-founder of Anasim Corporation, which commercializes power integrity and energy aware SoC (System on Chip) design tools.