Design and Analysis of Spiral Inductors

The book addresses the critical challenges faced by the ever-expanding wireless communication market and the increasing frequency of operation due to continuous innovation of high performance integrated passive devices. The challenges like low quality factor, design complexity, manufacturability, processing cost, etc., are studied with examples and specifics. Silicon on-chip inductor was first reported in 1990 by Nguyen and Meyer in a 0.8 μm silicon bipolar complementary metal oxide semiconductor technology (BiCMOS). Since then, there has been an enormous progress in the research on the performance trends, design and optimization, modeling, quality factor enhancement techniques, etc., of spiral inductors and significant results are reported in literature for various applications. This book introduces an efficient method of determining the optimized layout of on chip spiral inductor.

The important fundamental tradeoffs of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is also explored. The authors proposed an algorithm for accurate design and optimization of spiral inductors using a 3D electromagnetic simulator with minimum number of inductor structure simulations and thereby reducing its long computation time. A new multilayer pyramidal symmetric inductor structure is also proposed in this book. Being multilevel, the proposed inductor achieves high inductance to area ratio and hence occupies smaller silicon area.

Dr. Genemala Haobijam holds a Ph.D. in Electronics and Communication Engineering from Indian Institute of Technology Guwahati, India; M.Tech. degree in Microelectronics and VLSI Design from Shri Govindram Seksaria Institute of Technology and Science, Indore; and the B.E. degree in Electronics and Telecommunication Engineering from Shri Sant Gajanan Maharaj College of Engineering, Maharashtra. She was born in Imphal, Manipur, India. She has served as Assistant Professor at Indian Institute of Technology Mandi, Himachal Pradesh between 2010 and 2012. She has taught courses in Analog/Digital Circuits and System Design. She was awarded twice and given recognition for her teaching at Indian Institute of Technology Mandi. Her area of research and teaching interest focuses on analysis and design of Radio Frequency Integrated Circuits and Analog & Mixed Signal Circuits. She won the first prize in Design Contest of 22nd International Conference on VLSI Design, January 2009. She has published several papers in peer reviewed international journals and conferences. She has also worked for IBM India Pvt. Ltd. between 2009 and 2010. She is currently working at Samsung India Electronics Pvt. Ltd. She is a member of IEEE, IEEE Solid State Circuits Society, IEEE Women in Engineering.

Prof. Roy Paily received his B.Tech. degree in Electronics and Communication Engineering from College of Engineering, Trivandrum, India in 1990. He obtained the M.Tech. and Ph.D. from Indian Institute of Technology Kanpur and Indian Institute of Technology Madras in 1996 and 2004 respectively, in the area of Semiconductor Devices. Presently, he is working as a Professor in the Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati. Before joining academia, he worked as a Process Engineer in a hard disk manufacturing company. His research interests are VLSI devices/circuits and MEMS, and has published about 100 articles in journals and conferences. His team has taped out two silicon CMOS chips though Europractice IC Service under a Research and Development project "Special Manpower Development Project in VLSI Design and Related Software" sponsored by DIT, India. He has developed a web-based course, "Integrated Circuits Technology" under National program on Technology Enhanced Learning. “Digital VLSI Design Virtual Lab" is another online course developed through the initiative of MHRD. He is a member of IEEE and VLSI Society of India and a life member of ISSS and IETE.