Synthesizable Vhdl Design for Fpgas

Honed over two decades of teaching, this text is an excellent graded guide to very-high-speed integrated circuits hardware description language (VHDL), as implemented in two discrete field-programmable gate array (FPGA) platforms, one of which is widely used.

Dr. Eduardo Bezerra is a Researcher and Lecturer of Computer Engineering at Universidade Federal de Santa Catarina (UFSC), where he is with the Department of Electrical Engineering since 2010. He received his Ph.D. in Computer Engineering from the University of Sussex (Space Science Centre), England, UK, in 2002. His research interests are in the areas of embedded systems, computer architecture, reconfigurable systems (FPGAs), space applications, software & hardware testing, fault tolerance and microprocessor applications.

Djones Lettnin has Master’s in Electric Engineering at Catholic University of Rio Grande do Sul (2004), Brazil, and Sc.D. in Computer Engineering at the Eberhard Karls University of Tubingen (2009), Germany. In August 2011 he became Professor at Federal University of Santa Catarina, Brazil. Since August 2012 he is first coordinator of the Cadence Academic Network in Latin America. His main interests are in design and functional verification of hardware and embedded software with main focus on: modeling of embedded systems, digital design, verification based on assertions, semiformal and formal verification using model checking.