3D IC集成和封裝(英文影印版)（簡體書）

本書系統介紹用於電子、光電子和MEMS器件的2.5D、3D以及3D IC集成和封裝技術的前沿進展和演變趨勢，討論3D IC集成和封裝關鍵技術的主要工藝問題和解決方案。主要內容包括半導體工業中的集成電路發展，摩爾定律的起源和演變歷史，三維集成和封裝的優勢和挑戰，TSV制程與模型、晶圓減薄與薄晶圓在封裝組裝過程中的拿持晶圓鍵合技術、三維堆疊的微凸點製作與組裝技術、3D硅集成、2.5D/3D IC和無源轉接板的3D IC集成、三維器件集成的熱管理技術、封裝基板技術，以及存儲器、LED、MEMS、CIS 3D IC集成等關鍵技術問題，最後討論PoP、Fanin WLP、eWLP、ePLP等技術。本書主要讀者物件為微電子領域的研究生和從事相關領域的科學研究和工程技術人員。

劉漢誠（John H. Lau），伊利諾伊大學香檳分校理論與應用力學博士，不列顛哥倫比亞大學結構工程碩士，威斯康星大學麥迪遜分校工程力學碩士，菲爾萊狄更斯大學管理科學碩士，臺灣大學土木工程學士。

歷任臺灣欣興電子股份有限公司CTO、香港ASM太平洋科技有限公司高級技術顧問、臺灣工業技術研究院研究員、香港科技大學客座教授、新加坡微電子研究院MMC實驗室主任、惠普實驗室/安捷倫公司資深科學家（超過25年）。

擁有40多年的集成電路研發和製造經驗，專業領域包括集成電路的設計、分析、材料、工藝、製造、認證、可靠性、測試和熱管理等，目前研究領域為芯片異構集成、SiP、TSV、扇出/扇入晶圓/面板級封裝、MEMS、mini/ micro LED、3D IC集成、SMT和焊接力學等。

發表480多篇論文，發明30多項專利，舉辦 300多場講座，撰寫20多部教科書（涉及3D IC 集成、TSV、先進 MEMS 封裝、倒裝芯片 WLP、面積陣列封裝、高密度 PCB、SMT、DCA、無鉛材料、焊接、製造和可靠性等領域）。

ASME Fellow、IEEE life Fellow、IMAPS Fellow，積極參與ASME、IEEE和IMAPS的多項技術活動。獲得ASME、IEEE、SME等協會頒發的多項榮譽，包括IEEE/ECTC最佳會議論文（1989)、IEEE/EPTC最佳論文獎(2009)、ASME Transactions最佳論文獎(電子封裝雜志，2000)、IEEE Transactions最佳論文獎(CPMT，2010)、ASME/EEP杰出技術成就獎(1998)、IEEE/CPMT電子製造技術獎(1994)、IEEE/CPMT杰出技術成就獎(2000)、IEEE/CPMT杰出持續技術貢獻獎（2010）、SME電子製造全面卓越獎（2001）、潘文淵杰出研究獎（2011）、IEEE 繼續教育杰出成就獎（2000）、IEEE CPMT技術領域獎（2013）和 ASME 伍斯特·裡德·華納獎章（2015）等。

（1）源自工程實踐。基於作者40多年的集成電路研發和製造經驗，注重封裝工藝技術和實際解決方案，是工程應用的實用指南。

（3）聚焦核心技術。重點介紹TSV，應力傳感器，微凸點，RDL，硅中介層，芯片/芯片鍵合，芯片/晶圓鍵合，MEMS、LED、CMOS圖像傳感器的3D集成，以及熱管理、可靠性等關鍵技術問題。

（2）拓展國際視野。洞悉國際前沿技術方向和發展趨勢，熟悉先進技術和主流產品，有助於快速跟蹤、獨立發展相關核心技術。

（4）適合作為教材。源自作者開設的相關課程，配套PPT課件，內容系統全面，知識脈絡清晰，講解重點突出，有助於培養專業技術人才。

（5）應用領域廣泛。3D集成是集成電路技術發展的重要創新方向，是實現電子產品微型化、高性能、低成本、低功耗的重要手段。

3D IC integration is taking the semiconductor industry by storm. It has been (a) impacting chip suppliers, fabless design houses, foundries, integrated device manufacturers, out-sourced semiconductor assembly and test, substrates, electronics manufacturing services,original design manufacturers, original equipment manufacturers, material and equipment uppliers, universities, and research institutes; (b) attracting researchers and engineers from all over the world to go to conferences, lectures, workshops, panels, forums, and meetings to present their findings, exchange information, look for solutions, learn the latest technologies, and plan for their future; and (c) pushing the industry to build standards, infrastructures, and ecosystems for 3D IC integration.

This is a perfect storm! People and companies think that Moore’s law is going to take a bow soon and 3D IC integration is the next hot spot. In order to prepare for their future and have a competitive edge, they have been investing heavily in both human and physical resources for 3D IC integration. 3D IC integration is defined as stacking up thin chips/interposers in the third dimension with through-silicon vias (TSVs) and microbumps to achieve high performance and density, low power consumption, wide bandwidth, small form factor, and light weight. Thus TSVs, thin-wafer/chip handling, microbumps, assembly, and thermal management are the most important key enabling technologies for 3D IC integration.

Unfortunately, for most practicing engineers and managers, as well as scientists and researchers, TSVs, thin-wafer strength measurement and handling, microsolder bumping, redistribution layers (RDLs), interposers, chip-to-wafer bonding, wafer-to-wafer bonding, assembly, thermal management, reliability, and 3D IC integration with light-emitting diodes (LEDs), microelectromechanical systems (MEMS), and complementary metal-oxide semiconductor (CMOS) image sensors (CIS) are not well understood. Thus, there is an urgent need, in both industry and research institutes, to create a comprehensive book on the current state of knowledge of these key enabling technologies. This book is written so that readers can quickly learn about the basics of problem-solving methods and understand the tradeoffs inherent in making system-level decisions.

There are 10 major subjects in this book, namely, (1) 3D integration for semiconductor IC packaging (Chap. 1); (2) TSV electrical, thermal, and mechanical modeling and testing (Chap. 2); (3) stress sensors for thin-wafer handling and strength measurement (Chap. 3); (4) package substrate technologies (Chap. 4); (5) microsolder wafer bumping, assembly, and reliability (Chap. 5); (6) 3D Si integration, 2.5D/3D IC integration, and 3D IC integration with passive interposer (Chaps. 6, 7, and 8); (7) thermal management of 2.5D/3D IC integration (Chap. 9); (8) embedded 3D hybrid integration (Chap. 10); (9) 3D IC integration with LEDs, MEMS, and CIS (Chaps. 11, 12, and 13); and (10) 3D IC packaging (Chap. 14).

Chapter 1 briefly discusses 3D IC packaging, 3D IC integration, and 3D Si integration. The supply chains before and for the TSV eras are provided. The status of TSV high-volume manufacturing for CIS and MEMS products is presented.

Chapter 2 presents a high-frequency electrical analytic model and equations for a generic TSV structure. These equations have been verified in the frequency and time domains. Also,the equivalent thermal conductivity equations for a generic TSV are provided. These equations have been verified by 3D simulations of the TSV structure. Finally, Cu pumping and the keep-out-zone of Cu-filled TSVs are discussed.

Chapter 3 details the design, fabrication, and calibration of piezoresistive stress sensors. The application of stress sensors to thin-wafer handling is explored. Also, the application of stress sensors in wafer bumping is shown. Finally, the application of stress sensors in drop tests of embedded ultrathin chips is presented.

Chapter 4 presents the package substrates with build-up layers for flip chip 2.5D/3D IC integration applications. The coreless package substrate is also provided. Finally, the recent advances of package substrates with build-up layers are examined.

Chapter 5 discusses the wafer bumping, assembly, and reliability of 3D IC integration solder bumps at 25-μm, 20-μm, and 15-μm pitches. For each case, the test structure, solder material, under bump metallurgy (UBM), assembly condition, underfill, and reliability assessment are examined.

The next three chapters are specifically for 3D Si integration, 2.5D/3D IC integration, and 3D IC integration with passive interposer. Chapter 6 presents the overview, outlook, and challenges of 3D Si integration. Chapter 7 discusses the potential application of 3D IC integration, such as memory-chip stacking, wide I/O memory or logic-on-logic, wide I/O dynamic random-access memory (DRAM) or hybrid memory cube (HMC), wide I/O 2 and high bandwidth memory (HBM), and wide I/O interface (2.5D IC integration). Also, the fabrication of TSVs and RDLs are detailed. Finally, various thin-wafer handling methods are discussed. Chapter 8 presents three different structures of 3D IC integration with passive interposer. For each structure, the fabrication of the interposer and RDLs and final assembly of chips on both sides of the interposer are provided.

Chapter 9 presents the thermal management of 2.5D/3D IC integration. A new design which consists of an interposer with chips/heat spreader on its top side and chips with or without heat slugs on its bottom side is proposed. Also, a thermal performance comparison between 2.5D and 3D IC integration is provided. Finally, a thermal management system consisting of TSV interposers with embedded microchannels is presented.

Chapter 10 presents embedded 3D hybrid integration. Printed circuit boards using optical waveguides and embedded board-level optical interconnects are examined. Also, an embedded 3D hybrid integration system is proposed. Finally, a semi-embedded TSV interposer with a stress relief gap is presented.

The next three chapters are specifically for 3D IC integration with LEDs, MEMS, and CIS. Chapter 11 presents the status and outlook of Haitz’s law and four key segments of LED products. Also, the 2.5D/3D IC and LED integrations are presented. Finally, the thermal management of 3D IC and LED integration is presented. Chapter 12 presents 10 different designs and assembly processes of 3D IC and MEMS integration. Also, a low-temperature bonding of 3D MEMS packaging with solders is provided. Finally, recent developments in advanced 2.5D/3D IC and MEMS integration are examined. Chapter 13 presents the difference between front-illuminated (FI) CIS and back-illuminated (BI) CIS. Two examples (one is chip-to-wafer bonding and the other is wafer-to-wafer bonding) of 3D CIS and IC integration are discussed.

Chapter 14 presents 3D IC packaging, which includes chip stacking by wirebonding, package-on-package, fan-in wafer-level packaging, fan-out embedded wafer-level packaging, and embedded (rigid and flexible) panel-level packaging.

For whom is this book intended? Undoubtedly, it will be of great interest to three groups of specialists: (a) those who are active or intend to become active in research and development of the key enabling technologies of 3D IC integration such as TSVs, interposers, RDLs, thin-wafer handling, microbumps, assembly, and thermal management; (b) those who have encountered practical 3D IC integration problems and wish to understand and learn more methods for solving such problems; and (c) those who have to choose a reliable, creative, high-performance, high-density, low-power-consumption, wide-bandwidth, and cost-effective 3D IC integration technique for their products. This book can also be used as a text for college and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics and optoelectronics industry.

I hope that this book will serve as a valuable reference source for all those faced with the challenging problems created by the ever-increasing interest in 3D IC integration and 3D IC integration with LEDs, MEMS, and CIS. I also hope that it will aid in stimulating further research and development on key enabling technologies and more sound applications to 3D IC integration products.

The organizations that learn how to design and manufacture TSV, RDL, and microbump interconnects and thermal management in their 3D IC integration and packaging systems have the potential to make major advances in the electronics and optoelectronics industry,and to gain great benefits in performance, functionality, density, power, bandwidth, quality,size, and weight. It is my hope that the information presented in this book may assist in removing roadblocks, avoiding unnecessary false starts, and accelerating design, materials, process, and manufacturing development of key enabling technologies of 3D IC integration and packaging.

John H. Lau, Ph.D

Preface
1 3D Integration for Semiconductor IC Packaging
1.1 Introduction
1.2 3D Integration
1.3 3D IC Packaging
1.4 3D Si Integration
1.5 3D IC Integration
1.5.1 Hybrid Memory Cube
1.5.2 Wide I/O DRAM and Wide I/O 2
1.5.3 High Bandwidth Memory
1.5.4 Wide I/O Memory (or Logic-on-Logic)
1.5.5 Passive Interposer (2.5D IC Integration)
1.6 Supply Chains before the TSV Era
1.6.1 FEOL (Front-End-of-Line)
1.6.2 BEOL (Back-End-of-Line)
1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)
1.7 Supply Chains for the TSV Era-Who Makes the TSV
1.7.1 TSVs Fabricated by the Via-First Process
1.7.2 TSVs Fabricated by the Via-Middle Process
1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process
1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process
1.7.5 How About the Passive TSV Interposers
1.7.6 Who Wants to Fabricate the TSV for Passive Interposers
1.7.7 Summary and Recommendations
1.8 Supply Chains for the TSV Era-Who Does the MEOL, Assembly, and Test
1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process
1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process
1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process
1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers
1.8.5 Summary and Recommendations
1.9 CMOS Images Sensors with TSVs
1.9.1 Toshiba's DynastronTM
1.9.2 STMicroelectronics' VGA CIS Camera Module
1.9.3 Samsung's S5K4E5YX BSI CIS
1.9.4 Toshiba's HEW4 BSI TCM5103PL
1.9.5 Nemotek's CIS
1.9.6 SONY's ISX014 Stacked Camera Sensor
1.10 MEMS with TSVs
1.10.1 STMicroelectronics’ MEMS Inertial Sensors
1.10.2 Discera's MEME Resonator
1.10.3 Avago's FBAR MEMS Filter
1.11 References
2 Through-Silicon Vias Modeling and Testing
2.1 Introduction
2.2 Electrical Modeling of TSVs
2.2.1 Analytic Model and Equations for a Generic TSV Structure
2.2.2 Verification of the Proposed TSV Model in Frequency Domain
2.2.3 Verification of the Proposed TSV Model in Time Domain
2.2.4 TSV Electrical Design Guideline
2.2.5 Summary and Recommendations
2.3 Thermal Modeling of TSVs
2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction
2.3.2 Thermal Behavior of a TSV Cell
2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations
2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations
2.3.5 Summary and Recommendations
2.4 Mechanical Modeling and Testing of TSVs
2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si
2.4.2 Experimental Results on Cu Pumping during Manufacturing
2.4.3 Cu Pumping under Thermal Shock Cycling
2.4.4 Keep-Out-Zone of Cu-Filled TSVs
2.4.5 Summary and Recommendations
2.5 References
3 Stress Sensors for Thin-Wafer Handling and Strength Measurement
4 Package Substrate Technologies
5 Microbumps: Fabrication, Assembly, and Reliability
6 3D Si Integration
7 2.5D/3D IC Integration
8 3D IC Integration with Passive Interposer
9 Thermal Management of 2.5D/3D IC Integration
10 Embedded 3D Hybrid Integration
11 3D LED and IC Integration
12 3D MEMS and IC Integration
13 3D CMOS Image Sensor and IC Integration
14 3D IC Packaging
Index