Verilog HDL高級數字設計(第二版)(英文版)（簡體書）

本書依據數字集成電路系統工程開發的要求與特點，利用Verilog HDL對數字系統進行建模、設計與驗證，對ASIC/FPGA系統芯片工程設計開發的關鍵技術與流程進行了深入講解，內容包括：集成電路芯片系統的建模、電路結構權衡、流水、多核微處理器、功能驗證、時序分析、測試平臺、故障模擬、可測性設計、邏輯綜合、后綜合驗證等集成電路系統的前后端工程設計與實現中的關鍵技術及設計案例。書中以大量設計實例敘述了集成電路系統工程開發需遵循的原則、基本方法、實用技術、設計經驗與技巧。
本書既可作為電子與通信、電子科學與技術、自動控制、計算機等專業領域的高年級本科生和研究生的教材或參考資格，也可用于電子系統設計及數字集成電路設計工程師的專業技術培訓。

Michael D.Ciletti，科羅拉多大學電氣與計算機工程系教授。研究方向包括通過硬件描述語言進行數字系統的建模、綜合與驗證、系統級設計語言和FPGA嵌入式系統。其著作還有Digital Design，Fourth Edition(其翻譯版和影印版均由電子工業出版社出版)。作者曾在惠普、福特微電子和Prisma等公司進行VLSI電路設計的研發工作，在數字系統和嵌入式系統研究、設計等領域有豐富的研發和教學經歷。

1 Introduction to Digital Design Methodology
1.1 Design Methodology—An Introduction
1.2 IC Technology Options
1.3 Overview
References
2 Review of Combinational Logic Design
2.1 Combinational Logic and Boolean Algebra
2.2 Theorems for Boolean Algebraic Minimization
2.3 Representation of Combinational Logic
2.4 Simplification of Boolean Expressions
2.5 Glitches and Hazards
2.6 Building Blocks for Logic Design
References
Problems
3 Fundamentals of Sequential Logic Design
3.1 Storage Elements
3.2 Flip-Flops
3.3 Busses and Three-State Devices
3.4 Design of Sequential Machines
3.5 State-Transition Graphs
3.6 Design Example: BCD to Excess-3 Code Converter
3.7 Serial-Line Code Converter for Data Transmission
3.8 State Reduction and Equivalent States
References
Problems
4 Introduction to Logic Design with Verilog
4.1 Structural Models of Combinational Logic
4.2 Logic System, Design Verification, and Test Methodology
4.3 Propagation Delay
4.4 Truth Table Models of Combinational and Sequential Logic with Verilog
References
Problems
5 Logic Design with Behavioral Models of Combinational and Sequential Logic
5.1 Behavioral Modeling
5.2 A Brief Look at Data Types for Behavioral Modeling
5.3 Boolean Equation-Based Behavioral Models of Combinational Logic
5.4 Propagation Delay and Continuous Assignments
5.5 Latches and Level-Sensitive Circuits in Verilog
5.6 Cyclic Behavioral Models of Flip-Flops and Latches
5.7 Cyclic Behavior and Edge Detection
5.8 A Comparison of Styles for Behavioral Modeling
5.9 Behavioral Models of Multiplexers, Encoders, and Decoders
5.10 Dataflow Models of a Linear-Feedback Shift Register
5.11 Modeling Digital Machines with Repetitive Algorithms
5.12 Machines with Multicycle Operations
5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy?
5.14 Algorithmic State Machine Charts for Behavioral Modeling
5.15 ASMD Charts
5.16 Behavioral Models of Counters, Shift Registers, and Register Files
5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals
5.18 Design Example: Keypad Scanner and Encoder
References
Problems
6 Synthesis of Combinational and Sequential Logic
7 Design and Synthesis of Datapath Controllers
8 Programmable Logic and Storage Devices
9 Algorithms and Architectures for Digital Processors
10 Architectures for Arithmetic Processors
11 Postsynthesis Design Tasks
A Verilog Primitives
B Verilog Keywords
C Verilog Data Types
D Verilog Operators
E Verilog Language Formal Syntax
F Verilog Language Formal Syntax
G Additional Features of Verilog
H Flip-Flop and Latch Types
I Verilog-2001, 2005
J Programming Language Interface
K Web sites
L Web-Based Resources
Index