商品簡介
* Examines the various methods available for circuit protection, including coverage of the newly developed ESD circuit protection schemes for VLSI circuits.
* Provides guidance on the implementation of circuit protection measures.
* Includes new sections on ESD design rules, layout approaches, package effects, and circuit concepts.
* Reviews the new Charged Device Model (CDM) test method and evaluates design requirements necessary for circuit protection.
目次
Preface
1. Introduction
Background
The ESD Problem
Protecting against ESD
Outline of the Book
2. ESD Phenomenon
Introduction
Electrostatic Voltage
Discharge
ESD Stress Models
3. Test Methods
Introduction
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
Socket Device Model (SDM)
Metrology, Calibration, Verification
Transmission Line Pulsing (TLP)
Failure Criteria
Summary
4 Physics and Operation of ESD Protection Circuits
Introduction
Resistors
Diodes
Transistor Operation
Transistor Operation Under ESD Conditions
Electrothermal Effects
SCR Operation
Conclusion
5 ESD Protection Design Concepts and Strategy
The Qualities of Good ESD Protection
ESD Protection Design Methods
Selecting an ESD Strategy
Summary
6 Design and Layout Requirements
Introduction
Thick Field Device
NMOS Transistors (FPDs)
Gate-Coupled NMOS (GCNMOS)
Gate Driven nMOS (GDNMOS)
SCR Protection Device
ESD Protection Design Synthesis
Total Input Protection
ESD Protection Using Diode-Based Devices
Power Supply Clamps
BiPolar and BiCMOS Protection Circuits
Summary
7 Advanced Protection Design
Introduction
PNP Driven NMOS (PDNMOS)
Substrate Triggered NMOS (STNMOS)
NMOS Triggered NMOS (NTNMOS)
ESD for Mixed Voltage I/O
CDM Protection
SOI Technology
High Voltage Transistors
BiCMOS Protection
RF Designs
General I/O Protection Schemes
Design/layout Errors
Summary
8 Failure Modes, Reliability Issues, and Case Studies
Introduction
Failure Mode Analysis
Reliability and Performance Considerations
Advanced CMOS Input Protection
Optimizing the Input Protection Scheme
Designs for Special Applications
Process Effects on Input Protection Design
Total IC Chip Protection
Power Bus Protection
Internal Chip ESD Damage
Stress Dependent ESD Behavior
Failure Mode Case Studies
Summary
9 Influence of Processing on ESD
Introduction
High Current Behavior
Cross-section of a MOS Transistor
Drain-Source Implant Effects
P-Well Effects
N-Well Effects
Epitaxial Layers and Substrates
Gate Oxides
Silicides
Contacts
Interconnect and Metallization
Gate Length Dependencies
Silicon-On-Insulator (SOI)
Bipolar Transistors
Diodes
Resistors
Reliability Trade-Offs
Summary
10 Device Modeling of High Current Effects
Introduction
The Physics of ESD Damage
Thermal ("Second") Breakdown
Analytical Models Using the Heat Equation
Electrothermal Device Simulations
Conclusions
Circuit Simulation Basics, Approaches, and Simulations
Introduction
Modeling the MOSFET
Modeling Bipolar Junction Transistors
Modeling Diffusion Resistors
Modeling Protection Diodes
Simulation of Protection Circuits
Electrothermal Circuit Simulations
Conclusion
12 Conclusions
Long-term Relevance of ESD in ICs
State-of-the-art for ESD Protection
Current Limitations
Future Issues
