Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.
A Balanced Analysis of NoC ArchitectureAs the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain:


how the SoC and NoC technology works
why developers designed it the way they did
the system-level design methodology and tools used to configure the Spidergon STNoC architecture
differences in cost structure between NoCs and system-level networks


From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors – all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.
An Arsenal of Practical Learning Tools at Your DisposalThe book features a complimentary CD-ROM for practical training on NoC modeling and design-space exploration. It incorporates the award-winning System C-based On-Chip Communication Network (OCCN) environment, the only open-source network modeling and simulation framework currently available. With its consistent, comprehensive overview of the state of the art – and future trends – of NoC design, this indispensible text can help readers harness the value within the vast and ever-changing world of network-on-chip technology.

Towards Multicores: Technology and Software Complexity
Multicore Architecture, Algorithms and Applications
Complexity in Embedded Software
Technological Issues in Multicore Architectures
On-Chip Bus vs Network-on-Chip
Transition from On-Chip Bus to Network-on-Chip
Popular SoC Buses
Existing NoC Architectures
NoC Topology
On-chip Network topology
Multistage Interconnection Networks
Mesh and Torus
Chordal Rings
Other Constant Degree Topologies
The Spidergon STNoC Topology
Comparisons based on Topology Metrics
The Spidergon STNoC
Spidergon STNoC Interconnect Processing Unit
Switching Strategy
Communication Layering and Packet Structure
Routing Algorithms
Livelock, Starvation, and Deadlock
Protocol Deadlock Avoidance in Spidergon STNoC
Spidergon STNoC Building Blocks
Tile-based Architecture
SoC and NoC Design Methodology and Tools
SoC Design Methodology and Tools
NoC Design Methodology and Tools
The On-Chip Communication Network (OCCN)
Conclusions and Future Work
Enhanced IPU Programmability Portfolio
IPU Physical Design
IPU Design Tools
IPU Design and Verification Methodology