滿額折
Nano-cmos and Post-cmos Electronics ― Circuits and Design
商品資訊
ISBN13：9781849199995
出版社：Inst of Engineering & Technology
作者：Saraju P. Mohanty (EDT); Ashok Srivastava (EDT)
出版日：2016/08/31
裝訂／頁數：精裝／480頁
定價
：NT$ 7425 元若需訂購本書，請電洽客服 02-25006600[分機130、131]。
商品簡介
商品簡介
Continuing from volume 1, this volume outlines circuit- and system-level design approaches and issues for these devices.
Topics covered include self-healing analog/RF circuits; on-chip gate delay variability measurement in scaled technology; FinFET SRAM circuits; nanoscale FinFET devices for PVT aware SRAM; low leakage variability aware CMOS logic circuits; thermal effects in MWCNT VLSI interconnects; an accurate PVT-aware statistical logic library for nano-CMOS integrated circuits; SPICEless RTL design optimization of nano-electronic digital integrated circuits; power-delay trade-off driven optimal scheduling of CDFGs during high level synthesis; green on-chip inductors for three-dimensional integrated circuits; 3D NoC -- a promising alternative for tomorrow’s nano-system design; and DNA computing.
Topics covered include self-healing analog/RF circuits; on-chip gate delay variability measurement in scaled technology; FinFET SRAM circuits; nanoscale FinFET devices for PVT aware SRAM; low leakage variability aware CMOS logic circuits; thermal effects in MWCNT VLSI interconnects; an accurate PVT-aware statistical logic library for nano-CMOS integrated circuits; SPICEless RTL design optimization of nano-electronic digital integrated circuits; power-delay trade-off driven optimal scheduling of CDFGs during high level synthesis; green on-chip inductors for three-dimensional integrated circuits; 3D NoC -- a promising alternative for tomorrow’s nano-system design; and DNA computing.
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