商品簡介
Exploring new trends in computer technology, Corporal introduces an innovative and exciting concept: Transport Triggered Architecture (TTAs). Unlike most traditional architectures, where programmed operations trigger internal data transports, TTAs function through programming the data transports themselves. As a result the new architecture alleviates bottlenecks, allows for new code-generation optimizations and exploits hardware more efficiently. Founded on the author’s recent research, this book evaluates the attributes of different classes of architectures. It demonstrates how TTAs can be used as a template for automatic generation of application-specific processors and highlights their suitability for embedded system design. Several commercial TTA implementations have proven its concepts and advantages.
Features includes:
Complexity analysis of the data path of Instruction Level Parallel processors, particularly of VLIW (Very Long Instruction Word) and super-pipelined processors
Derivation of the transport triggering concept illustrating processor simplification
In-depth analysis of the architecture design space of TTAs and evaluation of architecture parameters
Examination of the control and pipelining of instruction, function and register units
Description of a trajectory for the automatic synthesis of TTAs for arbitrary applications written in a high-level language
Detailed description of a prototype TTA processor enabling the reader to design an embedded computer system with excellent cost-performance ratio
Microprocessor Architectures is cutting-edge text which will prove invaluable to both industrial hardware and software engineers involved in embedded system design and to postgraduate electrical engineering and computer science students. This clearly-structured reference demonstrates the versatility of TTAs and explores their influential role in the next generation of computer architecture.
目次
ARCHITECTURES: OVERVIEW AND COMPLEXITY.
Problem Statement.
Trends in Computer Architecture.
Bus Complexity.
Complexity of Instruction Level Parallel Processors.
TRANSPORT TRIGGERING CONCEPT.
From VLIW to TTA.
An Example Transport Triggered Processor.
THE DESIGN SPACE OF TRANSPORT TRIGGERED ARCHITECTURES.
Transport Design Space.
Function Unit Design Space.
Register Unit Design Space.
Exception Support.
ARCHITECTURE EVALUATION AND SYNTHESIS.
Evaluation of Architecture Parameters.
Automatic Synthesis of Transport Triggered Processors.
Summary and Perspective.
Appendices.
Glossary.
References.
Index.
