Formal Verification ― An Essential Toolkit for Modern Vlsi Design

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work.

Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity.

• Presents formal verification algorithms allowing users to gain full coverage without exhaustive simulation
• Provides discussion of formal verification tools and how they differ from simulation tools
• Teaches users how to glean insights into how models work to find initial bugs
• Presents valuable information from an Intel insider who shares his hard-won knowledge and solutions to complex design problems