滿額折
Resource Efficient Ldpc Decoders ― From Algorithms to Hardware Architectures
商品資訊
ISBN13：9780128112557
出版社：Academic Pr
作者：Vikram A. Chandrasetty; Sayed Mahfuzul Aziz
出版日：2017/12/15
裝訂／頁數：平裝／190頁
規格：23.5cm*19.1cm (高/寬)
定價
：NT$ 6750 元若需訂購本書，請電洽客服 02-25006600[分機130、131]。
商品簡介
商品簡介
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn:
- Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
- How to reduce computational complexity and power consumption using computer aided design techniques
- All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs
- Provides extensive treatment of LDPC decoding algorithms and hardware implementations
- Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware
- Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis
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