商品簡介
The 14 papers presented at the August 1999 workshop are grouped under the headings of architecture and applications, diagnosis and yield, memory testing topics, and new ideas in technology and design. The topics include unbalanced cache systems, failure mechanisms detected in memory chips during routine construction analysis, modeling and testing transistor faults in content-addressable memories, a comparative simulation study of four multilevel DRAMs, and low-power SRAM circuit design. No subject index. Annotation c. Book News, Inc., Portland, OR (booknews.com)
