滿額折
Recent Advances in PMOS Negative Bias Temperature Instability: Characterization and Modeling of Device Architecture, Material and Process Impact
商品資訊
ISBN13：9789811661198
出版社：Springer Nature
作者：Souvik Mahapatra(EDI)
出版日：2021/11/26
裝訂：精裝
規格：23.4cm*15.6cm*1.9cm (高/寬/厚)
定價
：NT$ 9859 元若需訂購本書，請電洽客服 02-25006600[分機130、131]。
商品簡介
商品簡介
1. Basic features, process dependence and variability of NBTI in p-MOSFETs 1.1. Introduction1.2. Measurement of NBTI kinetics1.2.1. Ultra-fast measure-stress-measure method1.2.2. Time evolution of stress and recovery1.2.3. Impact of measurement delay1.2.4. Voltage and temperature dependence 1.2.5. Duty cycle and frequency dependence1.2.6. Empirical estimation of end-of-life degradation1.3. Overview of NBTI process dependence 1.3.1. Impact of SiGe channel1.3.2. Impact of Nitrogen1.3.3. Impact of gate stack thickness scaling 1.3.4. Impact of fin dimension scaling1.3.5. Impact of layout1.4. NBTI in small area devices1.4.1. Stress and recovery kinetics1.4.2. Distribution of degradation1.4.3. Correlation of variability and variable NBTI1.4.4. Random Telegraph Noise1.5. Physical mechanism of NBTI - an overview1.6. Summary 2. NBTI kinetics modeling framework
2.1. Introduction2.2. Overview of NBTI modeling framework2.3. Generation and passivation of interface traps2.3.1. Double interface Reaction-Diffusion (RD) model2.3.2. Physical mechanism of defect depassivation2.3.3. A discussion on RD model parameters2.3.4. DCIV measurement method2.3.5. Prediction of DCIV data2.3.6. Analysis of Ge% and N% impact2.3.7. Comparison of continuum and stochastic frameworks2.4. Occupancy of generated interface traps2.4.1. Transient Trap Occupancy Model (TTOM)2.4.2. Validation of TTOM framework2.5. Hole trapping in pre-existing bulk traps2.6. Validation of TTOM enabled RD and hole trapping2.7. Time Dependent Defect Spectroscopy (TDDS) analysis2.8. Generation of bulk traps2.9. Validation of TTOM enabled RD and bulk trap generation2.10. Summary 3. Modeling of NBTI kinetics in HKMG Si and Si-capped SiGe p-MOSFETs
3.1. Introduction 3.2. Description of process splits3.3. Analysis of Gate First HKMG planar devices 3.3.1. DC stress and recovery kinetics3.3.2. Impact of measurement delay3.3.3. Nitrogen impact on NBTI parameters3.3.4. AC stress kinetics3.4. Analysis of mean stress-recovery kinetics from small area devices3.5. Process dependence of model parameters3.6. Estimation of end-of-life degradation 3.6.1. Calculation by empirical method3.6.2. Calculation by physical model3.6.3. Comparison of empirical and physical methods3.7. Analysis of Si-capped SiGe planar devices3.7.1. Stress and recovery kinetics3.7.2. Voltage acceleration factor3.7.3. Process dependence of model parameters 3.7.4. Estimation of end-of-life degradation3.8. Summary 4. Modeling of NBTI kinetics in HKMG Si and SiGe FDSOI MOSFETs 4.1. Introduction 4.2. Description of process splits 4.3. Analysis of measured data4.3.1. Time kinetics of stress and recovery4.3.2. Impact of Ge% and N%4.3.3. Impact of layout (STI to active spacing)4.3.4. Process dependence of model parameters4.4. Explanation of process dependence4.4.1. Impact of Ge% and N%4.4.2. Impact of layout effect 4.5. Estimation of end-of-life degradation 4.6. Summary
2.1. Introduction2.2. Overview of NBTI modeling framework2.3. Generation and passivation of interface traps2.3.1. Double interface Reaction-Diffusion (RD) model2.3.2. Physical mechanism of defect depassivation2.3.3. A discussion on RD model parameters2.3.4. DCIV measurement method2.3.5. Prediction of DCIV data2.3.6. Analysis of Ge% and N% impact2.3.7. Comparison of continuum and stochastic frameworks2.4. Occupancy of generated interface traps2.4.1. Transient Trap Occupancy Model (TTOM)2.4.2. Validation of TTOM framework2.5. Hole trapping in pre-existing bulk traps2.6. Validation of TTOM enabled RD and hole trapping2.7. Time Dependent Defect Spectroscopy (TDDS) analysis2.8. Generation of bulk traps2.9. Validation of TTOM enabled RD and bulk trap generation2.10. Summary 3. Modeling of NBTI kinetics in HKMG Si and Si-capped SiGe p-MOSFETs
3.1. Introduction 3.2. Description of process splits3.3. Analysis of Gate First HKMG planar devices 3.3.1. DC stress and recovery kinetics3.3.2. Impact of measurement delay3.3.3. Nitrogen impact on NBTI parameters3.3.4. AC stress kinetics3.4. Analysis of mean stress-recovery kinetics from small area devices3.5. Process dependence of model parameters3.6. Estimation of end-of-life degradation 3.6.1. Calculation by empirical method3.6.2. Calculation by physical model3.6.3. Comparison of empirical and physical methods3.7. Analysis of Si-capped SiGe planar devices3.7.1. Stress and recovery kinetics3.7.2. Voltage acceleration factor3.7.3. Process dependence of model parameters 3.7.4. Estimation of end-of-life degradation3.8. Summary 4. Modeling of NBTI kinetics in HKMG Si and SiGe FDSOI MOSFETs 4.1. Introduction 4.2. Description of process splits 4.3. Analysis of measured data4.3.1. Time kinetics of stress and recovery4.3.2. Impact of Ge% and N%4.3.3. Impact of layout (STI to active spacing)4.3.4. Process dependence of model parameters4.4. Explanation of process dependence4.4.1. Impact of Ge% and N%4.4.2. Impact of layout effect 4.5. Estimation of end-of-life degradation 4.6. Summary
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