Wafer-Level Testing and Test During Burn-In for Integrated Circuits

This analysis of methods for subjecting integrated circuits and semiconductor devices to electrical testing and stress testing will serve as a tutorial for engineers working with automatic test equipment. It shows how wafer-level testing during burn-in (WLTBI) helps lower product costs and increase quality in semiconductor manufacturing. Two introductory chapters offer background on testing and trends in WLTBI. The rest of the book details five methods, including resource-constrained testing of core-based SoCs, defect screening for mixed-signal SoCs, and power management by test-pattern ordering. The book also addresses the issue of testing next-generation products with previous-generation testers. A list of symbols and acronyms is included. Bahukudumbi is a quality and reliability test engineer at Intel Corporation. Chakrabarty teaches in the Department of Electrical and Computer Engineering at Duke University. Annotation c2010 Book News, Inc., Portland, OR (booknews.com)