Quality Conformance And Qualification Of Microelectronic Packages And Interconnects

All packaging engineers and technologists who want to ensure that they give their customers the highest quality, most cost-effective products should know that the paradigm has shifted. It has shifted away from the MIL-STDs and other government standards and test procedures that don't cost-effectively address potential failure mechanisms or the manufacturing processes of the product. It has shifted decisively towards tackling the root causes of failure and the appropriate implementation of cost-effective process controls, qualityscreens, and tests.

This book's groundbreaking, science-based approach to developing qualification and quality assurance programs helps engineers reach a new level of reliability in today's high-performance microelectronics. It does this with powerful...
* Techniques for identifying and modeling failure mechanisms earlier in the design cycle, breaking the need to rely on field data
* Physics-of-failure product reliability assessment methods that can be proactively implemented throughout the design and manufacture of the product
* Process controls that decrease variabilities in the end product and reduce end-of-line screening and testing


A wide range of microelectronic package and interconnect configurations for both single-and multi-chip modules is examined, including chip and wire-bonds, tape-automated (TAB), flip-TAB, flip-chip bonds, high-density interconnects, chip-on-board designs (COB), MCM, 3-D stack, and many more. The remaining package elements, such as die attachment, case and lid, leads, and lid and lead seals are also discussed in detail.

The product of a distinguished team of authors and editors, this book's guidelines for avoiding potential high-risk manufacturing and qualification problems, as well as for implementing ongoing quality assurance, are sure to prove invaluable to both students and practicing professionals.

For the professional engineer involved in the design and manufacture of products containing electronic components, here is a comprehensive handbook to the theory and methods surrounding the assembly of microelectronic and electronic components. The book focuses on computers and consumer electronic products with internal subsystems that reflect mechanical design constraints, cost limitations, and aesthetic and ergonomic concerns. Taking a total system approach to packaging, the book systematically examines: basic chip and computer architecture; design and layout; interassembly and interconnections; cooling scheme; materials selection, including ceramics, glasses, and metals; stress, vibration, and acoustics; and manufacturing and assembly technology. 1994 (0-471-53299-1) 800 pp.

INTEGRATED CIRCUIT, HYBRID, AND MULTICHIP MODULE PACKAGE DESIGN GUIDELINES: A Focus on Reliability --Michael Pecht

This comprehensive guide features a uniquely organized time-phased approach to design, development, qualification, manufacture, and in-service management. It provides step-by-step instructions on how to define realistic system requirements, define the system usage environment, identify potential failure modes, characterize materials and processes by the key control label factors, and use experiment, step-stress, and accelerated methods to ensure optimum design before production begins. Topics covered include: detailed design guidelines for substrate...wire and wire, tape automated, and flip-chip bonding...element attachment and case, lead, lead and lid seals--incorporating dimensional and geometric configurations of package elements, manufacturing and assembly conditions, materials selection, and loading conditions. 1993 (0-471-59446-6) 454 pp.

DR. MICHAEL PECHT is a ten-ured faculty member with a joint appointment in Systems Research and Mechanical Engineering, and the Director of the CALCE Electronic Packag-ing Research Center at the University of Maryland. He has an MS in electrical engineering and an MS and PhD in engineering mechanics from the University of Wisconsin. He is a Professional Engineer and an IEEE Fellow. He serves on the board of advisors for various companies and was a Westinghouse Professor. He is the chief editor of the IEEE Transactions on Reliability, on the board of advisors for IEEE Spectrum, and a section editor for the Society of Automotive Engineering.

DR. ABHIJIT DASGUPTA is a tenured faculty member with the CALCE Electronic Packaging Research Center at the University of Maryland.

DR. JOHN W. EVANS is a program manager of the Electronic Packaging Program for NASA Headquarters in Washington, D.C.

JILLIAN Y. EVANS is an aerospace engineer at the NASA Goddard Space Flight Center Facility in Greenbelt, Maryland

PHYSICAL ARCHITECTURE OF VLSI SYSTEMS Robert Hannemann, Allan D. Kraus, and Michael Pecht

Three-Dimensional Stacked Dies.

Cofired Ceramic Substrates.

Organic Laminated Substrates and Chip-on-Board.

High-Density Interconnects and Deposited Dielectrics.

Wire and Wirebonds.

Tape Automated Bonds.

Flip-Chip Bonds.

Device and Substrate Attachment.

Cases.

Leads.

Lead Seals.

Lid Seals.

Material and Product Evaluation Methods.

Rework Methods.

Bibliography.

Index.